The subject disclosure relates to a clockless superconducting logic family, and more specifically, to one or more direct current (“dc”) powered dynamic single flux quantum (“DSFQ”) logic circuits having one or more dynamic internal states.
Superconducting single flux quantum (“SFQ”) logic is considered an attractive alternative to complimentary metal-oxide-semiconductor (“CMOS”) technology in high performance computing (“HPC”) due to its high speed and a promise to reduce power in practical HPC applications (e.g., by about 2 orders of magnitude as compared to typical CMOS implementations), while using standard thin-film very-large-scale integration (“VLSI”) lithographic fabrication process.
However, most logic gates in the existing dc-powered SFQ logic families (e.g., rapid single flux quantum (“RSFQ”) and energy-efficient rapid single flux quantum (“ERSFQ”)) operate intrinsically as state machines (i.e., having internal logic states and requiring a clock signal to reset to a ground state after each clock cycle). Explicit use of clock signals in logic networks creates significant challenges for VLSI SFQ digital design, particularly concerning application of register transfer level (“RTL”) design paradigm, which is a cornerstone of VLSI digital design methodology. RTL paradigm assumes that large digital circuits can be subdivided into clocked registers holding all system states and clock-free, state-free logic networks of significant depth called combinational logic clouds.
Further, achieving dc-powered SFQ logic circuits that do not require a clock signal for operation is a difficult task. Traditionally internal logic states in SFQ superconducting logic gates are stored as currents circulating in superconducting loops that consist of superconducting wires (i.e., linear inductors) and Josephson junctions, the latter behaving as highly nonlinear superconducting inductors. More specifically, when a current through one of Josephson junctions in such storage loop temporary exceeds its critical current, that Josephson junction transitions to a resistive state and allows a discrete amount of magnetic flux (i.e., a single flux quantum, known as a “fluxon”) to enter or exit the storage loop, after which that Josephson junction can become superconducting again.
Switching of the Josephson junctions in a storage loop to implement a reset (i.e., a removal of a previously inserted fluxon) can be achieved through the application of one or more external signals (e.g., pulse-like currents originating from Josephson junctions switching events in one or more adjacent circuits). However, traditional SFQ circuitry does not comprise a storage loop that can remove a stored fluxon without the application of external signals; and therefore, cannot self-reset.